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A CMOS ADC architecture is presented that combines pipelined low pass ADCs with time interleaving to obtain sampling frequencies in the 3 to 6 GHz range with bandwidths of 1.5 to 3 GHz and 10-12 bits of resolution. The schematic design and performance simulations are included for a 180 nm CMOS process. The Time Interleaved Pipelined (TIP) ADC samples at 3.2(More)
Mixed-signal system design is a complex task with many levels of deliverables, includ-and process design kits. The ability to create mixed-signal design content has lagged behind digital design for decades, largely because the digital methodology has been able to make efficient use of design abstraction and implementation automation. In this work, we argue(More)
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