Ravindra Kuramkote

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Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization.(More)
Scalable shared memory multiprocessors traditionally use either a cache coherent non uniform memory access CC NUMA or simple cache only memory architecture S COMA memory architecture Recently hybrid architectures that combine aspects of both CC NUMA and S COMA have emerged In this paper we present two improvements over other hybrid architectures The rst(More)
Shared memory programs guarantee the correctness of concurrent accesses to shared data using interprocessor synchronization operations. The most common synchronization operators are locks, which are traditionally implemented via a mix of shared memory accesses and hardware synchronization primitives like test-and-set. In this paper, we argue that(More)
E cient synchronization is an essential component of parallel computing The designers of traditional multiprocessors have included hardware support only for simple operations such as compare and swap and load linked store conditional while high level synchronization primitives such as locks barriers and condition variables have been implemented in software(More)
Modern operating systems must support a wide variety of services for a diverse set of users. Designers of these systems face a tradeoo between functionality and performance. Systems like Mach provide a set of general abstractions and attempt to handle every situation, which can lead to poor performance for common cases. Other systems, such as Unix, provide(More)
Modern operating systems must support a wide variety of services for a diverse set of users. Designers of these systems face a tradeoo between functionality and performance. Systems like Mach provide a set of general abstractions and attempt to handle every situation, which can lead to poor performance for common cases. Other systems, such as Unix, provide(More)
In this paper we describe the design of the Avalanchemultiprocessor s shared memory subsys tem evaluate its performance and discuss problems associated with using commodity worksta tions and network interconnects as the building blocks of a scalable shared memorymultiprocessor Compared to other scalable shared memory architectures Avalanchehas a number of(More)
Minimizing communication latency in message passing multiprocessing systems is critical An emerging problem in these systems is the latency contribution costs caused by the need to percolate the message through the memory hierarchy at both sending and receiving nodes and the additional cost of managing consistency within the hierarchy This paper considers(More)
Conventional object-oriented programming systems allow application programmers to structure each application as a set of objects. They do not allow longterm storage of the objects, nor do they allow sharing and concurrency within the object spaces. Persistent object systems and object-oriented databases have been developed to address some of these(More)
As the gap between processor and memory speeds widens system designers will inevitably incorpo rate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance At the same time most communication subsystems are permitted access only to main memory and not a processor s top level cache As memory latencies(More)