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Developing ontologies to account for the complexity of biological systems requires the time intensive collaboration of many participants with expertise in various fields. While each participant may contribute to construct a list of terms for ontology development, no objective methods have been developed to evaluate how relevant each of these terms is to the(More)
With technology scaling, on-chip power dissipation and off-chip memory bandwidth have become significant performance bottlenecks in virtually all computer systems, from mobile devices to supercomputers. An effective way of improving performance in the face of bandwidth and power limitations is to rely on associative memory systems. Recent work on a(More)
Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell topologies are introduced to improve both the sense margin and the current ratio observed by the sense circuitry. These circuits utilize an additional transistor per cell in either a diode connected or gate connected manner and maintain leakage current immunity within the data(More)
—A field driven approach to STT-MRAM switching is proposed as a method for reducing the switching latency of an MTJ in high performance caches. An MRAM array model is presented to characterize the switching energy and maximum achievable reduction in energy using the field driven approach. The switching latency per bit is reduced by more than a factor of(More)
Scientists model physical phenomena by means of computer simulations that typically require iteratively solving large systems of linear equations. We discuss a novel method of solving these systems by exploiting recently developed mem-ristor technology. The proposed approach results in a 1500 × improvement in computational runtime, and an 8 .5 × reduction(More)
Over the past years, new memory technologies such as RRAM, STT-MRAM, and PCM have emerged. These technologies employ devices located within the metal layers of the integrated circuit, which are relatively fast, dense, and power efficient and can be considered as `memristors.' In this paper, we present these emerging memory technologies as enablers to the(More)
The physical dimensions of standard cells constrain the dimensions of power networks, affecting the on-chip power noise. An exploratory modeling methodology is presented for estimating power noise in advanced technology nodes. The models are evaluated for 14, 10, and 7 nm technologies to assess the impact on performance. Scaled technologies are shown to be(More)