Ravi Droopad

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We have demonstrated well-behaved accumulation-mode all oxide NMOSFETs with amorphous atomic-layer-deposited (ALD) LaAlO3 gate dielectric stacks on crystalline SrTiO3 substrates. A maximum drain current exceeding 10 mA/mm has been obtained on a 3.75μm-gate-length device, proving a very conductive channel can be formed at the oxide-oxide interface. Four(More)
investigation of Fermi energy level pinning mechanism on InAs and InGaAs clean surfaces Wilhelm Melitz, Jian Shen, Sangyeob Lee, Joon Sung Lee, Andrew C. Kummel, Ravi Droopad, and Edward T. Yu Materials Science and Engineering Program, University of California, San Diego, La Jolla, California 92093, USA Department of Chemistry and Biochemistry, University(More)
This paper describes a true enhancement mode RF power device with state-of-the-art performance operated at 3.5 Volts at 900 MHz. The performance was realized with a technology derived from the digital CGaAs/sup TM/ technology. The necessary device and process optimizations to adapt the digital technology for RF applications are discussed and results(More)
In recent years, fundamental interface issues have been overcome and GaAs MOS technology has advanced to the level of device fabrication. This development has been enabled by a molecular beam epitaxy (MBE) deposited Ga<sub>2</sub>O<sub>3</sub> template with the unique property of unpinning the Fermi level on GaAs, and a GdGaO dielectric layer which provides(More)
Formation of a contaminant free, flat, electrically passive interface to a gate oxide such as a-Al(2)O(3) is the critical step in fabricating III-V metal oxide semiconductor field effect transistors; while the bulk oxide is amorphous, the interface may need to be ordered to prevent electrical defect formation. A two temperature in situ cleaning process is(More)
The nucleation and passivation of oxide deposition was studied on defect-free GaAs (110) surfaces to understand passivation of surfaces containing only III-V heterobonds. The passivation process on GaAs (110) was studied at the atomic level using scanning tunneling microscopy while the electronic structure was determined by scanning tunneling spectroscopy(More)
The potential performance of implant free heterostructure In0 3Ga0 7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a(More)
We report data from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg = Vd = 1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage (Jg,limit) of 44 nA/cm, and on resistance (Ron) of 1640 Ω.μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicates their potential for scaling to(More)
In<sub>0.53</sub>Ga<sub>0.47</sub>As contains an intrinsically high electron mobility making it an attractive alternative semiconductor material for use in the channel region of MOSFET devices. The semiconductor/oxide interface can degrade device performance through interfacial roughness or formation of surface defects containing electronic trap states that(More)
Developments over the last 15 years in the areas of materials and devices have finally delivered competitive Ill-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/ Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel(More)