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This paper describes an integrated pair of tools - one designed for Timing Verification and the other designed for Logic Simulation - in a multi-level, mixed mode description environment. Historically, Logic Simulators and Timing Verifiers have been used for different types of verification, due to an inherent weakness in each. Particularly, Logic simulators(More)
A general algorithm is presented for consistency checking between schematics. A transistor level schematic is partitioned into functional blocks by tracing direct current paths. The first level consistency check is performed on the directed graphs constructed from these functional blocks. A recursive, graph matching algorithm is introduced to find signal(More)
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