Raqibul Hasan

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Recent studies have shown that memristor crossbar based neuromorphic hardware enables high performance implementations of neural networks at low power and in low chip area. This paper presents circuits to train a cascaded set of memristor crossbars representing a multi-layered neural network. The circuits presented implement back-propagation training and(More)
An ageing population is now the leading concern for higher healthcare costs due to more cases of chronic illnesses. Telemedicine systems based on modern Information and Communication Technology (ICT) are expected to play a pivotal role in alleviating the pressure on health care services. Environmental factors have also profound impact on health condition of(More)
This study examines the design of several novel specialized multicore neural processors. Systems based on SRAM cores and memristor devices were examined. Detailed circuit simulations were used to ensure that the systems could be compared accurately. Two types of memristor cores were examined: digital and analog cores. Novel circuits were designed for both(More)
This paper describes a novel memristor-based neuromorphic circuit that can be used for ex-situ training of multi-layer neural network algorithms. The presented ex-situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. This is possible because the proposed circuit is capable of(More)
This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed using this neuron circuit. These neuromorphic circuits are capable of learning both linearly and non-linearly separable logic(More)
Neuromemristive systems (NMSs) are gaining traction as an alternative to conventional CMOS-based von Neumann systems because of their greater energy and area efficiency. A proposed NMS accelerator for machine-learning tasks reduced power dissipation by five orders of magnitude, relative to a multicore reduced-instruction set computing processor.
Specialized multi-core architectures can provide significant speedups for neural network applications. In this study, we examined the on-chip routing network bandwidth requirements for such architectures processing large multi-layered feed forward neural networks in a pipelined manner. Two on-chip routing network topologies were examined: mesh networks and(More)
Reversible multiple-valued logic circuit has several advantages over reversible binary logic circuit. In this paper, we propose a method of minimization of Galois field sum of products (GFSOP) expression for non-reversible quinary logic function. We also propose a method of reversible realization of quinary GFSOP expression as cascade of quinary reversible(More)