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This paper provided a study of two different high-level approaches to interconnecting complex processing elements on an FPGA, a compile-time-scheduled, time-multiplexed interconnect and a packet-switched interconnect with communication patterns determined at run-time. One of the distinguishing features of field-programmable gate arrays is the user's ability(More)
Primary cultured rat cerebellar granule neurons underwent apoptosis when switched from medium containing 25 mM K+ to one containing 5 mM K+. N-methyl-D-aspartate (NMDA) protected granule neurons from apoptosis in medium containing 5 mM K+. Inhibition of apoptosis by NMDA was blocked by the phosphatidylinositol 3-kinase (PI 3-kinase) inhibitor LY294002, but(More)
—How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional(More)
Optimized hardware for propagating and checking software-programmable metadata tags can achieve low runtime overhead. We generalize prior work on hardware tagging by considering a generic architecture that supports software-defined policies over metadata of arbitrary size and complexity; we introduce several novel microarchitectural optimizations that keep(More)
The ability of ethanol to interfere with insulin-like growth factor 1 (IGF-1)-mediated cell survival was examined in primary cultured cerebellar granule neurons. Cells underwent apoptosis when switched from medium containing 25 mM K+ to one containing 5 mM K+. IGF-1 protected granule neurons from apoptosis in medium containing 5 mM K+. Ethanol inhibited(More)
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The graph structures are large, and the applications need regular access to a large, data-dependent portion of the graph for each operation (e.g., the algorithm may need to walk the(More)
We show that, with the VPR implementation of Pathfinder, perturbations of initial conditions may cause critical paths to vary over ranges of 17-110%. We further show that it is not uncommon for VPR/Pathfinder to settle for solutions that are >33% slower than necessary. These results suggest there is room for additional innovation and improvement in FPGA(More)
— In nanowire-based logic, the semiconducting material (e.g., Si, GaN, SiGe) is grown into individual nanowires rather than being part of the substrate. This offers us the opportunity to stack multiple layers of nanowires to create a three-dimensional logic structure which has high quality semiconductors in all vertical layers. We detail a feasible(More)