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In this paper is described a software technique allowing to detect soft errors occurring in processor-based digital architectures. The detection mechanism is based on a set of rules allowing the transformation of the target application into a new one, having same functionalities but being able to identify bit-flips arising in memory areas as well as those(More)
Fault tolerant circuits are currently required in several major application sectors. Besides and in complement to other possible approaches such as proving or analytical modeling whose applicability and accuracy are significantly restricted in the case of complex fault tolerant systems, fault-injection has been recognized to be particularly attractive and(More)
This work presents probabilistic methods for testability analysis at RTL and their use to evaluate the sensitivity of a digital circuit to Single Event Upsets (SEUs). A new probabilistic testability metric is proposed, in order to evaluate if the possible changes caused by SEUs are ignored or propagated by the dynamic behavior of the circuit. The new(More)
—An approach to study the effects of single event upsets (SEU) by fault injection performed at system-level is presented. It is illustrated by results obtained on two different versions of a matrix multiplication algorithm, one standard and the second with fault tolerance capabilities. The final goal of this work is to validate fault tolerance techniques(More)
This paper investigates an approach to study the effects of upsets on the operation of microprocessor-based digital architectures. The method is based on the injection of bitf lips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built(More)
This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented(More)
This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line " injection " and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral(More)
This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated , and is particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results from software and(More)