Ranko Sredojevic

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—This paper analyzes the energy efficiency of different transmit equalizer driver topologies. Dynamic impedance modulation is found to be the most energy-efficient mechanism for transmit pre-emphasis, when compared with impedance-maintaining current and voltage-mode drivers. The equalizing transmitter is implemented as a digital push–pull(More)
This paper presents a system identification technique for generating stable compact models of typical analog circuit blocks in radio frequency systems. The identification procedure is based on minimizing the model error over a given training data set subject to an incremental stability constraint, which is formulated as a semidefinite optimization problem.(More)
Digital push-pull impedance-modulating (RM) pre-emphasis driver overcomes the power overhead of equalization in voltage-mode (VM) drivers, improving the output stage efficiency ∼2–3x. A compact, fully-digital RAM-DAC implementation with pattern lookup compensates both duty-cycle distortion and driver nonlinearity, while providing a(More)
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-speed links are particularly hard to analyze because of the complex interplay of device/circuit parasitics and channel filtering operation. In this paper we introduce(More)
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Abstract—This paper presents a system identification technique for generating(More)
In this work we aim to strike a balance between performance, power consumption and design effort for complex digital signal processing within the power and size constraints of embedded systems. Looking across the design stack, from algorithm formulation down to accelerator microarchitecture, we show that a high degree of flexibility and design reuse can be(More)
Many integrated communication systems today are constrained by either throughput or power dissipation. Cases from high-speed I/O interfaces in processors and routers to low-power radios in cell phones and sensors force designers to tackle one of the two dual problems – optimizing the overall data rate with given power constraints or minimizing the power for(More)
Much work has been done within the optimization and circuit communities related to the optimization of individual circuit blocks [1-2]. Both equation-based and simulation-based optimization methods have enjoyed recent success for certain problems [3-4]. However, the best of these newest methods are still painfully overwhelmed by the sheer size of the design(More)
Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-1. While applicable to data rates up to 10(More)