Ramya Muralidharan

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The performance of RNS relies heavily on efficient implementation of residue arithmetic units. In this paper efficient multi-modulus squarer architectures for the moduli 2<sup>n</sup>&#x2212;1, 2<sup>n</sup> and 2<sup>n</sup>+1 are presented. Two variants of multi-modulus squarer architectures, i.e., fixed and variable multi-modulus architectures, are(More)
Modulo 2<sup>n</sup>+1 squaring has been used in various applications like cryptography and Fermat number transform. Arithmetic modulo 2<sup>n</sup>+1 is also known to be the most time critical among the three residue channels in the prevalent {2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup>+1} based residue number system (RNS). In order to speed up modulo(More)
An area-efficient diminished-1 modulo 2<sup>n</sup>+1 multiplier with radix-4 modified Booth encoding is proposed. The proposed approach minimizes the number of Booth encoder and Booth decoder blocks required for partial product generation. Its correction factor is decomposed into a multiplier-dependent dynamic bias and a multiplier-independent static bias.(More)
Residue Number System (RNS) is often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. To sustain the competitive advantages of RNS over two's complement system in pervasive computing platforms, the hardware cost of parallel modulo arithmetic operations must be lowered. In this paper, new low power(More)
Hard multiple generation is the bottleneck operation in radix-8 Booth encoded modulo 2<sup>n</sup>&#x2212;1 and modulo 2<sup>n</sup>&#x002B;1 multipliers. In this paper, fast hard multiple generators for the moduli 2<sup>n</sup>&#x2212;1 and 2<sup>n</sup>&#x002B;1 are proposed. They are implemented as parallel-prefix structures based on the simplified carry(More)
Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication. Two multi-modulus multipliers that reuse the hardware resources amongst the modulo 2<sup>n</sup>-1, modulo 2<sup>n</sup> and modulo(More)
High-speed modulo multipliers are essential elements in RNS datapath. Booth recoding algorithm can be used to improve the performance of the multiplier by reducing the number of partial products. In radix-8 Booth encoding, the number of partial products is reduced to one-third. However, the inevitable carry propagation adder required to generate the hard(More)
In this paper, we propose programmable serial- in parallel-out LSB-first and MSB-first modular multipliers for elliptic curve cryptosystems (ECCs). The proposed multipliers can operate in any arbitrary field GF(2<sup>m</sup>) such that m is less than a maximum field order M. A linear array of processing elements is designed with a parallel switching(More)