Ramsey W. Haddad

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We present a recursive method for generating layout for VLSI chips which combines the flexibility of gate array and standard cell layout with the control and density of custom layout. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is(More)
Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay(More)
Integrated circuit design has principally focused on achieving performance goals (e.g., speed) with minimal cost (e.g., area) using as little design time as possible. To help designers achieve these goals computer-aided design tools have traditionally focused on tools which improve performance, reduce area, and improve productivity. In the beginning of this(More)