Ramayya Kumar

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In this article we present a structured approach to formal hardware veriication by modelling circuits at the register-transfer level using a restricted form of higher-order logic. This restricted form of higher-order logic is suucient for obtaining succinct descriptions of hierarchically designed register-transfer circuits. By exploiting the structure of(More)
The HOL system is a powerful tool for proving higher-order formulae. However, proofs have to be performed interactively and only little automation using tactics is possible. Even though interaction is desirable to guide major and creative backward proof steps of complex proofs, a deluge of simple sub-goals may evolve which all have to be proven manually in(More)
This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant(More)
In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels, so that the overall specification is correct with respect(More)
In this paper a practical methodology for formally verifying RISC cores is presented. Using a hierarchical model which reflects the abstraction levels used by designers of real RISC processors, proofs between neighboring levels are performed for simplifying the verification process. The proofs are performed by showing that each instruction is executed(More)
This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to post-synthesis ver-iication techniques our approach is constructive in a sense that the proof is(More)
Usually, digital circuits are split up into control and data path as there are speciic synthesis methods for controllers and operation units. However, all known approaches to hardware veriication which make use of this fact, model the operation unit also as a nite-state machine. This leads to enormous space requirements which limit the applicability of(More)
J Abstract. Verification of digital circuits in higher-order logic often requires the proof of temporal propositional logic formulae. The implementation of decision procedures for this logic or finite-state machines is however not very easy within the HOL system, since it requires the proof of certain fixpoint theorems and a creation of a new theory based(More)