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Invited Paper In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of " least energy computation. " We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state. The(More)
Goal: Position the U.S. at the forefront of communications and computation capability beyond the physical and conceptual limitations of current technologies. Description and Scientific Rationale: Moore's Law refers to the empirical observation made in 1965 that computer processing power, based on semiconductor integrated circuits, doubles about every 18(More)
This article presents the ERD Working Group's collective judgment with respect to the long-term potential of nanoscale memory and logic devices to replace silicon-based CMOS logic or baseline memory technology. It does not judge their potential to supplement or complement CMOS. The intent is thus prescriptive, not prescriptive: to provide a technically(More)
Emerging research device technologies might first appear in special applications that can extend conventional general-purpose processors along one of several axes. These applications could optimize the performance of future workloads such as recognition, mining, and synthesis by using the unique nonlinear output characteristics associated with the emerging(More)
This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive(More)