Ralph K. Cavin

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ion for electron transport switching devices. For example, the field-effect transistor (FET) can be thought of as consisting of two wells (source and drain) separated by a barrier (channel). ZHIRNOV et al.: LIMITS TO BINARY LOGIC SWITCH SCALING—A GEDANKEN MODEL 1935 In this paper, we consider implications for device design at the highest levels of(More)
This article presents the ERD Working Group's collective judgment with respect to the long-term potential of nanoscale memory and logic devices to replace silicon-based CMOS logic or baseline memory technology. It does not judge their potential to supplement or complement CMOS. The intent is thus prescriptive, not prescriptive: to provide a technically(More)
The search for alternate information processing technologies to sustain Moore’s Law improvements beyond those attainable by scaling of charge-based devices encompasses several key technologies. Some of these technologies were explored at the Third Workshop on Silicon Nanoelectronics and Beyond (SNB III) held at the National Science Foundation in Washington(More)
Emerging research device technologies might first appear in special applications that can extend conventional general-purpose processors along one of several axes. These applications could optimize the performance of future workloads such as recognition, mining, and synthesis by using the unique nonlinear output characteristics associated with the emerging(More)
Morphic architectures embrace a broad class of mixed-signal systems that focus on a particular application and draw inspiration for their structure from the application. In some cases, processing is carried out in the analog domain, offering orders-of-magnitude improvement in performance and power dissipation, albeit with reduced accuracy. The emergence of(More)