Ralph H. J. M. Otten

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A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is(More)
Advancing technology drives design technology andthus design automation (EDA). How to model interconnect, ho w to handle degradation of signal integrity and increasing power density are changing now, and have ledto integrating logic and layout synthesis. Agressive gatesizing to control timing has become part of any modernback-end. F rom 0:13µ and down,(More)
We present an analytic formula for repeater insertion in globalinterconnects that simultaneously minimizes silicon device areaand power dissipation for a given performance ¿{crit}/K where ¿{crit}is the minimum possible delay along a global interconnect, withrepeaters inserted, and 0 < K ¿ 1. Given a certain wire geometry(width and layer assignment) and a(More)
The problem of allocating area to modules at the highest level of a top-down decomposition is treated in this paper. A theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane. The dutch metric is introduced to transform netlist information - if available - into a distance matrix. This metric is flexible enough to(More)
In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off.(More)
This paper surveys the more important oorplan models and their u s e in the backend of chip design. Floorplans are here considered as data structures that capture the relative p o-sitions o f o b je c t s i n a p lane. This is in correspondance with how they were introduced in design automation in the early eighties: as a generalization of placement, that(More)
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for <i>statistical timing analysis</i> and parametric yield prediction of digital(More)
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout " fabric " scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead , power and ground are essentially " pre-routed " all over the die. By a clever arrangement of(More)
Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming(More)