Ralph H. J. M. Otten

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A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is(More)
In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off.(More)
The problem of allocating area to modules at the highest level of a top-down decomposition is treated in this paper. A theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane. The dutch metric is introduced to transform netlist information - if available - into a distance matrix. This metric is flexible enough to(More)
Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming(More)
We present a technology mapping procedure in which an area-delay trade-off curve is constructed at each node using matches found for different decompositions of the node. This information is used effectively to find implementations that meet delay constraints while reducing area. The procedure combines state-of-the-art mapping procedures, in which a graph(More)
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for <i>statistical timing analysis</i> and parametric yield prediction of digital(More)
The concept of the genealogical approach to the layout problem is presented. The system pursues the idea of flexible modules and is capable of dealing with arbitrarily complex tasks. The genealogical tree of the system provides a mainframe for organizing the information flow. Results of the system routines are described in terms of transitions between(More)
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout “fabric” scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially “pre-routed” all over the die. By a clever arrangement of(More)
Chip industry obeys a number of laws, various kinds of laws. Mathematical laws if accurate models can be formulated, physical laws, especially solid state physics, obtained by observation and induction, chemical laws pertinent for the manufacturing processes, economical and judicial laws that concern such industries. The most famous and most cited law of(More)
This paper surveys the more important oorplan models and their use in the backend of chip design. Floorplans are here considered as data structures that capture the relative positions of objects in a plane. This is in correspondance with how they were introduced in design automation in the early eighties: as a generalization of placement, that is the(More)