Rajshekar Kalayappan

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In this paper, we present the design of a new Java based, cycle-accurate, heterogeneous architectural simulator, Tejas. Tejas is a trace driven simulator, which is platform-independent. It can simulate binaries in any ISA and corresponding to virtually any operating system. It can itself run on virtually any machine. It is one of the fastest cycle accurate(More)
Reliability is quickly becoming a primary design constraint for high-end processors because of the inherent limits of manufacturability, extreme miniaturization of transistors, and the growing complexity of large multicore chips. To achieve a high degree of fault tolerance, we need to detect faults quickly and try to rectify them. In this article, we focus(More)
We are moving into an era where large SoCs will have a portfolio of different kinds of cores and accelerators. Many of these computational elements might be designed by third parties. In this setting, it is beneficial to collect accurate runtime information such that we can diagnose performance problems, verify and report correctness issues, and collect(More)
Lock-based parallel programs are easy to write. However, they are inherently slow as the synchronization is blocking in nature. Non-blocking lock-free programs, which use atomic instructions such as compare-and-set (CAS), are significantly faster. However, lock-free programs are notoriously difficult to design and debug. This can be greatly eased if the(More)
Mission critical applications face a security risk when they use third-party ICs for their speed and/or technology benefits. SecCheck is an architectural framework that securely incorporates fast, untrusted third-party cores (3PCs). It takes a comprehensive approach, providing for all of the different traditional fault tolerance techniques, to verify the(More)
Soft errors have become a serious cause of concern with reducing feature sizes. The ability to accommodate complex, Simultaneous Multithreading (SMT) cores on a single chip presents a unique opportunity to achieve reliable execution, safe from soft errors, with low performance penalties. In this context, we present <i>FluidCheck</i>, a checker architecture(More)
We study the problem of intruder tracking with non-stealthy sensors, i.e., sensors whose ON/OFF state can be detected by an intruder, sometimes in advance. The sensor field is assumed to be operating with a sleep schedule to conserve energy. Both motion sensors and presence sensors are considered. We provide a rigorous basis for the study of this scenario(More)
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