Rajesh Rajaraman

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algorithms time complexity ROM space special condition modulo adder size PI wg 4 > n2 no n*M PI wg 4 2 yes 2 " PI O(n) &n " , no M New algorithm 000~ nl O(n) no <M 1001 in the figure are the same. Each cell in the tree performs the findno algorithm. In the diagram, the RNS representation is used as input to the first level of cells in pair, i.e. is the(More)
Switching circuits with thyristor controlled reactors are used in high power systems for static VAR control and flexible AC transmission. These circuits can exhibit highly nonlinear behavior because the thyristor switch off time depends on the circuit state. This paper shows how to understand and predict damping and resonance in a basic thyristor controlled(More)
  • A Wrzyszcz, D Caban, E A Dagless, S Andraros, H Ahmad, A Bayoumi +7 others
  • 1999
It can be seen that the Vinnakota and Rao converters using cascade subtractors exhibit more delay than the Andraros and Ahmad design. Note that in the Andraros and Ahmad design, the full adders needed can be reduced [10] by noting that one of the inputs B in (4) is a constant 1 or 0 for n LSB's, which we have not considered in the above evaluation in (5a).(More)
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