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Noise estimation and avoidance are becoming critical,must have' capabilities in today's high performance IC design.An accurate yet efficient crosstalk noise model whichcontains as many driver/interconnect parameters as possible,is neccesary for any sensitivity based noise avoidanceapproach. In this paper, we present a complete analyticalcrosstalk noise(More)
<italic>Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources(More)
Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability(More)
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of " dominant leakage states " and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over(More)
Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical(More)
We present a methodology for the design and analysis of power grids in the PowerPC&#8482; microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC&#8482; 750 microprocessor is presented.
Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create(More)
We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and(More)
Due to higher power and faster switching frequencies a very robust power distribution network is required. To achieve this the power distribution network needs to be modeled accurately at different stages of the design cycle. We present a methodology for the design and analysis of power distribution networks. The methodology covers the need for power grid(More)