Rajeev Jayaraman

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FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements(More)
In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures(More)
State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One of the consequences of the banked organization is that all of the I/O objects that are placed within a bank must use " compatible " I/O standards. The compatibility of I/O(More)
— Platform FPGAs have introduced complex reconfig-urable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration(More)
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