# Rajashekhar Reddy M

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- Sriharsha Veeramachaneni, Lingamneni Avinash, Rajashekhar Reddy M, M. B. Srinivas
- 2006 6th International Workshop on System on Chip…
- 2006

In this paper, the design of a binary to residue converter architecture based on {2<sup>k</sup>-1, 2<sub>k</sub> 2<sup>k</sup>+l} modulo set is presented. New highly-parallel schemes using (p,2) compressors are described for computing the integer modulo operation (X mod m), where m is restricted to the values 2<sup>k</sup>plusmn1, for any value of k>1… (More)

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