Rajashekhar Modugu

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—Cryptographic algorithms such as International Data Encryption Algorithm(IDEA) have found various applications in secure transmission of the data in networked instru-mentation and distributed measurement systems. Modulo 2 n + 1 multiplier and squarer play a pivotal role in the implementation of such crypto-algorithms. In this work, an efficient hardware(More)
Modulo 2 n +1 multiplier is one of the critical components in applications in the area of digital signal processing, data encryption and residue arithmetic that demand high-speed and low-power operation. In this paper, an efficient hardware architecture of modulo 2 n + 1 multiplier is proposed and validated to address the demand. The proposed modulo 2 n +1(More)
Modulo 2 n + 1 multiplier and squarer are critical components in various applications such as secure communications in networked instrumentation and distributed measurement systems, data encryption and residue arithmetic that increasingly demand high-speed and low-power operations. In this paper, an efficient hardware architecture of modulo 2 n + 1(More)
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