Rajasekaran Chandrasekaran

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This paper proposes a new D flip-flop configuration based on differential cascode voltage switch with pass-gate logic. The circuit is able to reduce the transition time from the input to output. The flip-flop was implemented in 0.18 mum CMOS technology. The flip-flop was simulated using HSPICE to assess the performance and was further evaluated by(More)
This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-flop. The filter has been implemented in a 0.18 mum/ 1.8 V CMOS technology for a decimation(More)
An all-digital CMOS ultra-wideband (UWB) pulse generator with 3&#x2013;5GHz frequency range is presented in this paper. The pulse generator is tunable in both amplitude and bandwidth to meet the FCC spectral mask requirement. The circuit is implemented in 0.13 &#x03BC;m CMOS process with a core area of 0.024 mm<sup>2</sup> and achieving an energy efficiency(More)
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