Raja Gaurav

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SRAM Bit-Cell Sleep technique is extensively used in processors to minimize SRAM leakage power. However, magnitude of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper analyzes influence of design parameters like VCCMIN_RET, DVS, ITD and NBTI on effectiveness of SRAM(More)
VMIN induced Yield Loss is increasing in nanoscale CMOS era, due to quest for performance at low power. SRAM arrays are the largest contributor to this variety of yield loss due to a wide VMIN distribution. To minimize yield loss due to wide SRAM VMIN distribution, authors propose the use of error correction techniques and redundancy. Measured VMIN(More)
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