Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been clearly demonstrated on 8 " wafers with statistical data. Large I ON at low V DD are possible according to TCAD simulations but awaits verification. V DD scaling will greatly benefit from low (effective) band gap energy materials,… (More)
—We demonstrate L g = 100 nm high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm Al 2 O 3 layer grown by atomic layer deposition. The MOSFETs with L g = 100 nm exhibit V T = 0.2 V (E-mode), R ON = 370 Ω · μm, S = 105 mV/dec, DIBL = 100 mV/V, and g m_ max = 1720… (More)
As the overall economy and semiconductor industry emerges from one of the worst recessions in years, it is time to take stock of EDA challenges and its future. This panel will focus on which challenges will surge and dominate EDA over the course of next several years and which challenges we can sell short.