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Abstract Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8” wafers. Large ION at low VDD are possible according to TCAD simulations but awaits verification. VDD scaling will greatly benefit from low (effective) band gap energy, which may be provided by(More)
This paper reports InAs quantum-well (QW) MOSFETs with record transconductance (gm,max = 1.73 mS/μm) and high-frequency performance (fT = 245 GHz and fmax = 355 GHz) at Lg = 100 nm. This record performance is achieved by using a low Dit composite Al2O3/InP gate stack, optimized layer design and a high mobility InAs channel. This work is significant because(More)
We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO<inf>2</inf> high-k gate dielectrics exhibited low C-V hysteresis (&#x226A;10 mV), interface trap density (7.5&#x00D7;10<sup>10</sup>), and gate leakage current(More)
Abstract Electron mobility on (100) and (110) planar FETs and SOI FinFETs was evaluated. It is experimentally demonstrated that the (110) sidewall of FinFETs does not present a drawback in terms of electron mobility – contrary to results obtained on (110) planar MOSFETs. This is comprehensively explained by a combination of first principles and empirical(More)
Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit(More)
Lower operation current and voltage are strongly required for scaled RRAM devices with high density memory cell arrays. As the lower operation current reduces the size of the conductive filament, stable high speed endurance performance of RRAM device becomes a challenging issue. In this work, for the first time, we demonstrate 1&#x03BC;A,(More)
After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and(More)
We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al<inf>2</inf>O<inf>3</inf>-Si<inf>3</inf>N<inf>4</inf>-&#x201C;Tunnel-oxide (TO)&#x201D;-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO<inf>2</inf>, HfSiO, Al<inf>2</inf>O<inf>3</inf>, Si<inf>3</inf>N<inf>4</inf>) and(More)
Phase identification and the degree of crystallization in ultra-thin HfO<sub>2</sub> has been extremely challenging due to the &gt; 5 nm range order sensitivity of X-ray diffraction which is not sufficient to detect nanocrystallization. Yet detailed knowledge of the nanostructure is critical to the development of accurate performance models. Therefore,(More)