Learn More
Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8 " wafers. Large I ON at low V DD are possible according to TCAD simulations but awaits verification. V DD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type(More)
We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO<inf>2</inf> high-k gate dielectrics exhibited low C-V hysteresis (&#x226A;10 mV), interface trap density (7.5&#x00D7;10<sup>10</sup>), and gate leakage current(More)
Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit(More)
After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and(More)
Lower operation current and voltage are strongly required for scaled RRAM devices with high density memory cell arrays. As the lower operation current reduces the size of the conductive filament, stable high speed endurance performance of RRAM device becomes a challenging issue. In this work, for the first time, we demonstrate 1&#x03BC;A,(More)
Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and(More)
Band engineering in TANOS (TaN-Al<sub>2</sub>O<sub>3</sub>-Si<sub>3</sub>N<sub>4</sub>-SiO<sub>2</sub>-Silicon) Flash memory utilizing an interfacial dipole is demonstrated for the first time. A dipole layer at the tunnel oxide/charge storage layer interface leads to increase in programming speed while maintaining good retention and endurance. Using a(More)
—We demonstrate L g = 100 nm high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm Al 2 O 3 layer grown by atomic layer deposition. The MOSFETs with L g = 100 nm exhibit V T = 0.2 V (E-mode), R ON = 370 Ω · μm, S = 105 mV/dec, DIBL = 100 mV/V, and g m_ max = 1720(More)
This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent I<inf>on</inf>-I<inf>off</inf> characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, V<inf>t</inf>(More)