Rainer Schlör

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This paper reports experiences and results gained during the evaluation of the visual formalism STD as speciication method for formal veriication, performed in cooperation with industrial partners. The visual formalism STD (Symbolic Timing Diagrams) was developed continuously since 1993 by OFFIS as a speciication method, which satisses several needs: (1) It(More)
This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal–verification environment for VHDL leading to a novel methodology based on the combination of(More)
This paper presents three novel aspects of sysbem-level hardware design: A graphical specification language called STD (Symbolic Timing Diagrams), a design methodology with formal verification of each development step, and a powerful automatic verification tool, which owes its effciency to sophisticated optimization techniques exploiting the properties of(More)
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