Rainer Schlör

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In this paper we present a novel approach to the specification and verification of system-level hardware designs. It is based on Timing Diagrams, a graphical specification language with an intuitive semantics, which is especially appropriate for the description of asynchronous distributed systems such as hardware designs. Timing Diagrams and their semantics(More)
This paper reports experiences and results gained during the evaluation of the visual formalism STD as speciication method for formal veriication, performed in cooperation with industrial partners. The visual formalism STD (Symbolic Timing Diagrams) was developed continuously since 1993 by OFFIS as a speciication method, which satisses several needs: (1) It(More)
VHDL/S, the language being developed and employed in the FORMAT project, integrates VHDL, temporal logic, and, as graphical formalisms, timing diagrams and state based specifications into a single framework for specification and verification of reactive behaviour, in particular on the system level. Timing diagrams, like the temporal logic they are based(More)
To guarantee real-time behavior of an embedded application, a schedulability analysis can be used. Such an analysis requires the worst case execution time (WCET) of the application. While several academic approaches to conservatively bound the WCET have been proposed in the last decade, common practice in industry remains simulation and software tests. One(More)
In the formal verification domain the use of monitors represents a powerful technique where model I/O sequences are monitored and triggers are raised to allow a simplification in the construction of formal properties. This reduces the chances of incorrect system specifications and can sometimes reduce also the actual model checking time. The drawback of(More)