Rainer Schlör

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In this paper we present a novel approach to the specification and verification of system-level hardware designs. It is based on Timing Diagrams, a graphical specification language with an intuitive semantics, which is especially appropriate for the description of asynchronous distributed systems such as hardware designs. Timing Diagrams and their semantics(More)
This paper reports experiences and results gained during the evaluation of the visual formalism STD as speciication method for formal veriication, performed in cooperation with industrial partners. The visual formalism STD (Symbolic Timing Diagrams) was developed continuously since 1993 by OFFIS as a speciication method, which satisses several needs: (1) It(More)
This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal–verification environment for VHDL leading to a novel methodology based on the combination of(More)
Service-oriented architectures (SOA) have received much attention for providing specification principles in order to develop flexible and interoperable software systems. This is achieved by concentrating on " non-technical " concepts of the application domain in order to structure software systems in a functional, business process-oriented manner-thereby(More)