Rafael B. Schivittz

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Many of the nanometer CMOS challenges are seriously compromising the gains attained with technology scaling, mainly impacting the yield and the circuit reliability. To cope with these problems, new design methodologies are necessary to improve the robustness of the circuits. Given the overheads associated with the traditional fault-tolerant approaches,(More)
Reliability in advanced CMOS devices is a critical issue that can supersede the benefits of technology shrinking process. The Probabilistic Transfer Matrix (PTM) is the basis of more common reliability evaluation models. This work presents a probabilistic model for stuck-on faults in combinational logic gates, considering the individual fault probability of(More)
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