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Technology, performance, and computer-aided design of three-dimensional integrated circuits
The overall 3D integration process flow is discussed, as well as specific technological challenges and the issues they present to circuit designers and how these issues may be tackled during the placement, routing, and layout stages of physical design.
Interconnect limits on gigascale integration (GSI) in the 21st century
This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands and one potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance.
System-level performance evaluation of three-dimensional integrated circuits
The wire (interconnect)-length distribution of 3-D integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution).
Morphology and Bond Strength of Copper Wafer Bonding
The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
It is found that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.
Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)
  • A. Rahman, R. Reif
  • Engineering
    Proceedings of the IEEE International…
  • 6 June 2001
In this paper, we examine the thermal issues in 3-D ICs by system-level modeling of power dissipation and analytical and numerical modeling of deviceand package-level heat removal. We find that for
Recrystallization of amorphized polycrystalline silicon films on SiO2: Temperature dependence of the crystallization parameters
This paper presents a theoretical and experimental study of the recrystallization behavior of polycrystalline silicon films amorphized by self‐implantation. The crystallization behavior was found to
Microstructure evolution and abnormal grain growth during copper wafer bonding
Evolution of microstructure morphologies and grain orientations of Cu–Cu bonded wafers during bonding and annealing were studied by means of transmission electron microscopy, electron diffraction,
Copper Wafer Bonding
Three-dimensional integrated circuits: performance, design methodology, and CAD tools
Three-dimensional integration technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated, according to a suite of circuit design tools developed for this analysis.