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A Framework for QoS Adaptive Grid Meta Scheduling
TLDR
In this paper, we introduce the notion of scheduling based on "availability", and provide a framework (AG-MetS) for QoS adaptive grid meta scheduling. Expand
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REDEFINE: Runtime reconfigurable polymorphic ASIC
TLDR
We propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. Expand
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Synthesis of application accelerators on Runtime Reconfigurable Hardware
TLDR
In this paper we define the architecture of Runtime Reconfigurable Hardware (RRH) as the platform for application acceleration. Expand
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Hardware Solution for Real-Time Face Recognition
TLDR
The objective of this paper is to come up with a scalable modular hardware solution for real-time face recognition on large databases. Expand
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Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
TLDR
We carry out extensive micro-architectural exploration for accelerating core kernels like Matrix Multiplication (MM) (BLAS-3) for LU and QR factorizations. Expand
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High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit
TLDR
We propose a fully parallel 64K point radix-44 FFT processor which is optimized for low latency without compromising in area and throughput. Expand
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RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router
TLDR
In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. Expand
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Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems
TLDR
We present an energy efficient and scalable FFT architecture for computation of FFTs of sizes 64 to 4K point, which can be dynamically reconfigured to adapt to specifications of different standards. Expand
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An Incessantly Coherent Cache Scheme for SharedMemory Multithreaded
An incessantly coherent cache consistency protocol is proposed in this paper. The protocol supports limitless sharing and obviates the need to invalidate shared cache lines by automatically selfExpand
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Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design
TLDR
In this paper, we present acceleration of Level-1 (vector operations), Level-2 (matrix-vector operations) BLAS through algorithm architecture co-design on a Coarse-grained Reconfigurable Architecture (CGRA). Expand
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