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Energy-aware mapping for tile-based NoC architectures under performance constraints
TLDR
In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. Expand
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Energy- and performance-aware mapping for regular NoC architectures
TLDR
In this paper, we present an algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. Expand
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"It's a small world after all": NoC performance optimization via long-range link insertion
TLDR
In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Expand
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DyAD - smart routing for networks-on-chip
TLDR
We present and evaluate a novel routing scheme called DyAD which combines the advantages of both deterministic and adaptive routing schemes. Expand
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
TLDR
We enumerate several related research problems in the design of NoCs. Expand
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Key research problems in NoC design: a holistic perspective
TLDR
We provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Expand
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Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
TLDR
Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known a priori. Expand
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On-chip traffic modeling and synthesis for MPEG-2 video applications
TLDR
The objective of this paper is to introduce self-similarity as a fundamental property exhibited by the bursty traffic between on-chip modules in typical MPEG-2 video applications. Expand
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Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
TLDR
This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI Simulation results show about 40% savings for a real video application. Expand
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FARM: Fault-aware resource management in NoC-based multiprocessor platforms
TLDR
In this paper, we address the problem of run-time resource management in non-ideal multiprocessor platforms where communication happens via the Network-on-chip (NoCs) approach. Expand
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