• Publications
  • Influence
Transient power supply current monitoring—A new test method for CMOS VLSI circuits
TLDR
A new method for testing digital CMOS integrated circuits using the transient power supply current as a window of observability into the circuit switching behavior and introducing a method for isolating normal switching transients from those which result from defects. Expand
Testing of static random access memories by monitoring dynamic power supply current
  • S. Su, R. Makki
  • Engineering, Computer Science
  • J. Electron. Test.
  • 1 August 1992
TLDR
It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells and a new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. Expand
A high level language implementation of a general purpose telemetry system for biomedical applications
This paper describes a general purpose biomedical telemetry system consisting of an implantable VLSI chip and an RS232 compatible remote telemetry receiver. The implant supports a variety ofExpand
Transient power supply current testing of digital CMOS circuits
TLDR
The physical experimental results show i/sub DDT/ to be effective in detecting disturb faults in SRAMs and drain/ source opens in general CMOS logic structures. Expand
i/sub DDT/ test methodologies for very deep sub-micron CMOS circuits
TLDR
Preliminary results on these three test methods using a relatively small transistor-level sample circuit are reported, and are not intended to imply any feasibility in a production environment. Expand
An improved method for i/sub DDT/ testing in the presence of leakage and process variation
TLDR
Results show that the method is capable of improving the detection capability of threshold-based i/sub DDT/ testing for faults that would otherwise go undetected due to leakage and process variation. Expand
Dynamic Power Supply Current Testing of CMOS SRAMs
TLDR
The design and implementation of a dynamic power supply current sensor which is used to detect SRAM faults such as disturb faults as well as logic cell faults and can supplement the observability associated with any test algorithm by using the sensor as a substitute for the read operations. Expand
Dynamic power supply current testing of CMOS SRAMs
TLDR
A dynamic power supply current sensor is used to detect SRAM-specific faults such as disturb faults as well as logic cell faults and offers on-chip detectability of faults. Expand
Power supply current detectability of SRAM defects
  • J. Liu, R. Makki
  • Materials Science, Computer Science
  • Proceedings of the Fourth Asian Test Symposium
  • 23 November 1995
TLDR
The results show that the power supply current can be used to detect cell shorts, cell opens, and disturb-type pattern sensitivity and the effect of total current leakage in thepower supply, which is proportional to SRAM size, on the power Supply current detectability of SRAM cell defects. Expand
SRAM test using on-chip dynamic power supply current sensor
  • J. Liu, R. Makki
  • Engineering
  • Proceedings. International Workshop on Memory…
  • 24 August 1998
We present an overview of power supply current testing of SRAMs and propose a test method to improve the CMOS SRAM test efficiency by using on-chip dynamic power supply current sensors. It is shownExpand
...
1
2
3
4
5
...