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Heavy Ion, High-Energy, and Low-Energy Proton SEE Sensitivity of 90-nm RHBD SRAMs
We measure the sensitivity of different 90-nm SRAM cells to single-event upsets (SEUs) caused by heavy ions, high energy protons, and low energy protons. We discuss radiation hardened by designExpand
Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing
We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements ofExpand
Predicting the Single-Event Error Rate of a Radiation Hardened by Design Microprocessor
We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and addExpand
A method for efficient Radiation Hardening of multicore processors
This paper describes a method for developing Radiation Hardened by Design (RHBD) multicore processor Integrated Circuits (ICs) that meet specific single-event error rate targets in space environmentsExpand
At-Speed SEE Testing of RHBD Embedded SRAMs
We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell UpsetsExpand
An age-aware library for reliability simulation of digital ICs
A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account keyExpand
ASIC by design: automated design of digital signal processing application-specific integrated circuits
Comparing the optimized results to the baseline, we are achieving typically 10-20/spl times/ improvement in PDA. This allows gap closure to approach the optimization of a full custom design processExpand
Total Ionizing Dose Characterization of a Custom Front-End SoC for Antenna Arrays in 32nm SOI CMOS
A full-custom SoC was fabricated in 32nm SOI CMOS for the monolithic signal digitization of the signal coming from a 16-channel antenna array. In particular, the chip included multiple 3-bit 32GSpsExpand
MSP Liberator ASIC Design Flow Produces Full Custom Performance Required for Next Generation Military Electronics
Next generation military systems and other national security applications require advanced digital signal processing electronics implemented in highly optimized ASICs with Mission Specific ProcessingExpand
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