R. Vijay Sai

  • Citations Per Year
Learn More
Present System on Chip (SoC) complexity has brought new challenges in volume of test pattern, low power testing and area complexity. This also shows that implementing huge test pattern and its corresponding storage space are the major problems. Due to this large number of test patterns the data transition time is also increased. This paper considers this(More)
Applications with large amount of data level parallelism can benefit from General Purpose based Graphics Processing Units (GPGPUs) because of better energy efficiency and performance compared to a CPU. Due to GPGPUs’ impressive computing throughput and memory bandwidth, many applications with enough parallelism can take advantage of acceleration using(More)
Low power testing in VLSI has emerged as a standard idea in today's electronics industry. The need for low power is root for a major pattern shift where power consumption has become a significant concern while comparing with performance and area. This work explores XOR network with Linear Feedback Shift Register (LFSR), which is having different tap(More)
  • 1