R. Tutundjian

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MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that can efficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problem solutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly(More)
This paper describes fault simulation algorithms for the MARS hardware accelerator designed and developed at the AT&T Bell Laboratories. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation(More)
In this paper, we describe a hardware multiple delay logic simulator that incorporates efficient timing analyses algorithms for event cancellations, spike and race analyses and oscillation detection. The algorithms are implemented on a set of reconfigurable processors, arranged in a pipelined configuration. Spike analysis is accomplished by dynamic pulse(More)
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