R. T. Naayagi

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In this paper, a technique for synthesizing binary tree structure of a non-regenerative logic circuit functionality is proposed, that achieves delay optimization by reducing the logic depth. It also helps in minimizing the resources needed to implement the logic tree structure with FPGA as target technology. Although it is a technology–independent scheme,(More)
This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the(More)
This paper presents the modelling, simulation and hardware evaluation of a grid tied inverter suitable for wind energy conversion systems. The grid-tied wind power converter converts the energy harvested from wind to DC through a permanent magnet synchronous generator using a simple diode rectifier and then converts it back to AC using a pulse width(More)
In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical(More)
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