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—In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L e) of 25 nm (oxide thickness = 1 1 nm), 50 nm (oxide thickness = 1 5 nm) and 90 nm (oxide thickness = 2 5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in(More)
Independent control of front and back gate in double gate (DG) devices can be used to merge parallel transistors in noncritical paths. This reduces the effective switching capacitance and, hence, the dynamic power dissipation of a circuit. However, efficient design of large-scale circuits with DG devices is not well explored due to lack of proper modeling(More)
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