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The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for &lt;11ps global clock skew in a 435mm<sup>2</sup> die. The cache and control sections contain 2 primary clock domains and 11 clock spines. A pipelined de-skew logic tolerant to inter-domain clock uncertainties manages the core and(More)
The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global(More)
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm<sup>2</sup> die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to(More)
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