R. Holwill

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An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads.(More)
A novel interconnect scheme is presented which reduces the number of pads required by electrical verniers to measure mask misalignment. It makes the use of a shift register no longer necessary to keep the pad count to a reasonable number and the process is only required to support the fabrication of diodes. The vernier can be measured using any test(More)
A new interconnect scheme is proposed which reduces the pad to tooth ratio for passive electrical verniers. This design is based upon the maximum theoretical number of direct connections between N pads which is N(N-1)/2. This concept is developed further and it is demonstrated that the use of diodes can reduce the ratio to N (N-1): N. Some experimental(More)
INTRODUCTION The limitations of doped polycrystalline silicon and aluminium as gate and interconnect materials are well known. The relatively low resistivity of metal silicides, together with their oxidisability has made them attractive candidates for replacing polycrystalline silicon gates and interconnects. At present silicide formation is achieved by(More)
The design and implementation of a CMOS-compatible high-voltage process is described. It is shown that small changes can be made in an established n-well process to produce both high-voltage p- and n- channel power LDMOS transistors. These changes do not affect the performance of the low-voltage devices, and result in breakdown voltages of 50 volts for the(More)
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