R. G. Gordon

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The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A wellcontrolled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V(More)
In this letter, we demonstrate a gate-all-around single-wall carbon nanotube field-effect transistor. This is the first successful experimental implementation of an off-chip gate and gate-dielectric assembly with subsequent deposition on a suitable substrate. The fabrication process and device measurements are discussed in the letter. We also argue in how(More)
In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW(More)
In this work, we report on a 3D device fabrication technology achieved by applying a novel anisotropic wet etching method. By aligning channel structures along different crystal orientations, high performance 3D InGaAs devices with different channel shapes such as fins, nanowires and waves have been demonstrated. With further optimizing off-state leakage(More)
InAs gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time by a top-down approach <sup>[1-3]</sup>. Thanks to the well-controlled nanowire release process and the novel ALD high-k/metal gate stack process, InAs nFETs with channel length (L<sub>ch</sub>) ranging from 380 to 20 nm and nanowire width (W<sub>NW</sub>) from 60(More)
Amorphous LaAlO3 films were deposited on hydrogen-terminated silicon substrates by atomic layer deposition (ALD) at 300 o C. The precursors were lanthanum tris(N,N’-diisopropylformamidinate), trimethylaluminum (TMA) and water. Capacitance-voltage measurements made on ALD MoN/LaAlO3/Si stacks showed humps especially at low frequencies. They were effectively(More)
By realizing a high-quality epitaxial La<sub>2</sub>O<sub>3</sub>/ GaAs(111)A interface, we demonstrate GaAs CMOS devices and integrated circuits including nMOSFETs, pMOSFETs, CMOS inverters, NAND and NOR logic gates and five-stage ring oscillators for the first time. As an exercise of III-V CMOS circuits on a common substrate with a common gate dielectric,(More)
In this paper, 20nm-80nm channel length (L<sub>ch</sub>) InGaAs gate-all-around (GAA) nanowire MOSFETs with record high on-state and off-state performance have been demonstrated by equivalent oxide thickness (EOT) and nanowire width (W<sub>NW</sub>) scaling down to 1.2nm and 20nm, respectively. SS and DIBL as low as 63mV/dec and 7mV/V have been(More)
In this paper, the first air-stable n-type and p-type chemical doping in graphene via charge transfer have been demonstrated, and shown that the doping does not deteriorate the majority carrier mobility. The top-gated graphene structures have been further fabricated and demonstrated p-n junction in graphene nanoribbon (GNR) devices.
We have demonstrated well-behaved accumulation-mode all oxide NMOSFETs with amorphous atomic-layer-deposited (ALD) LaAlO<inf>3</inf> gate dielectric stacks on crystalline SrTiO<inf>3</inf> substrates. A maximum drain current exceeding 10 mA/mm has been obtained on a 3.75&#x00B5;m-gate-length device, proving a very conductive channel can be formed at the(More)