R. Canegallo

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Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC(More)
Background. As interest on wearable computing [1] increases , researchers are looking for new materials to use as a support for electronics. A fabric substrate is very appealing: it is elastic and extensible [2], supported by a well known technology and produced at low-cost. State of the art. Some smart pressure-sensors interfacing with a flexible substrate(More)
Reconfigurable computing is well suited for wireless applications because of its capability to adapt to changing communication protocols. However, as technology scales, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents different buffered switches mixing low and high threshold transistors(More)
Chip-to-chip interconnection, based on wireless communication by capacitive coupling was investigated. This innovative approach will considerably reduce the pitch of the pin and strongly help in the implementation of a dense network of interconnects, while improving inter-chip bandwidth and power dissipation. The 3D integration technology based on aligned(More)
This standard flash-EEPROM contains 1M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6Mb memory with 257Mb/cm 2 array density. High-density digital storage techniques for floating gate devices (>8 levels) require the use of feedback in the programming loop (pulse and verify method) and substantially(More)
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system(More)
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