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This paper presents a high-performance reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. This is achieved by combining pipelining concept with novel skew core key scheduling method and compared with previous illustrated encryption algorithms. The DES design is implemented on Xilinx Spartan-3e Field Programming Gate(More)
The complex business strategies of cloud services make Job scheduling a challenging issue. The mapping of user jobs onto a computing resource to achieve maximum benefit, satisfying the varying QoS of user's jobs, is the ultimate goal of a cloud provider. As this scheduling problem belongs to the family of combinatorial problems, it cannot be formulated as a(More)
With the emergence of Grid technologies, the problem of scheduling tasks in heterogeneous systems has been arousing attention. Task scheduling is a NP-complete problem[5] and it is more complicated under the Grid environment. To better use tremendous capabilities of Grid system, effective and efficient scheduling algorithms are needed. In this paper, we are(More)
Task scheduling in Grid becomes more complicated when user demands different QoS. In this paper, we have proposed QoS Guided Weighted Mean Time Min-Min Max-Min Selective heuristic for QoS based task scheduling. The heuristic takes single QoS parameter as requirements of tasks for deciding the match between resources and tasks. The heuristic also considers(More)
One of the important aspects in digital video applications is spatial and temporal characteristic. A very little progress has been achieved on spatio-temporal modeling of video data. In this paper, we present a fuzzy spatio-temporal model for video content description that supports spatio-temporal queries. Fuzzy definitions and membership functions of(More)
This paper deals with crosstalk analysis of a CMOS gate driven capacitively and inductively coupled interconnect. Alpha Power Law model of MOS - transistor is used to represent a transistor in CMOS- driver. This is combined with a transmission line based coupled RLC-model of interconnect to develop a composite driver interconnect load (DIL) model for(More)
Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product(More)