R. B. Staszewski

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We propose and demonstrate the first RF digitally-controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip fully-compliant quad-band GSM transceiver realized in a 90 nm digital CMOS process. Frequency tuning is achieved through digital control of an array of standard n-poly/n-well MOSCAP devices. The finest varactor step size(More)
We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase/frequency detector. When implemented in a deep-submicron(More)
We present the first 90-nm digital CMOS RF power amplifier. This PA contains a large array of NMOS switches, and performs a direct digital-to-RF-amplitude conversion, filtering and buffering in a fully-integrated GSM/EDGE transmitter. Power control is fully digital. 40% efficiency is obtained at 10-dBm output power from 1.4 V and it occupies 0.005 mm/sup 2/.
We present a novel approach for built-in self-testing (BIST) of an RF wireless transmitter. This approach, based on fully-digital hardware and on software algorithms, allows the testing of the transmitter's analog/RF circuitry while providing low-cost replacements for the costly traditional RF tests. The testing approach is structural in nature and(More)
Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. Conf, sec. 15.1, pp. 268-269, 527, 2004; K. Muhammad and R.B. Staszewski, Proc. IEEE Intl. Symp. on Circ. and Sys., sec. ASP-L29.5, 2004) in which an input RF signal is converted to current waveform, down-converted and integrated on a sampling capacitor. A(More)
We present a fully integrated analog path for a 3 G polar transmitter in 90 nm CMOS. It includes a quad band Digitally Controlled Oscillator providing modulation for the phase data and a single stage Digital Pre-Power Amplifier that combines the phase and amplitude signals while providing the dynamic range for WCDMA. The chip, with integrated LDOs, consumes(More)
A fully-digital frequency synthesizer for RF wireless applications has recently been proposed. It replaces the conventional VCO with a digitally-controlled oscillator with sufficiently fine frequency resolution. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop(More)
We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital architecture that makes it insensitive to NMOS and PMOS mismatches. The time(More)
A fully digital implementation for an RF built-in self-test (RF BIST), incorporated within a digital RF processor (DRPtrade)-based system-on-chip (SoC), is presented. The proposed mechanism serves as an on-chip built-in modulation-noise estimation-module (BIMNEM) for the testing of the 2.4 GHz local oscillator of a Bluetooth transceiver offered by Texas(More)
Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of such complex ICs that accept input close to the RF carrier frequency and are analyzed for receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband(More)