R. B. Anna

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This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost(More)
This paper describes the challenges of designing RF integrated circuits using the advanced RFCMOS technology. Following an overview of the RFCMOS process, design challenges for low cost, high performance RFICs and their integration issues are discussed. Discussions show that these challenges can be addressed through innovative circuit and system design,(More)
We show that the low-frequency noise (LFN) of 90 nm nFETs can increase considerably due to hot-carrier stress. Measurements reveal noise degradation for both linear and saturation regions of operation. The use of deuterium processing retards the noise degradation and improves the noise lifetime by more than 20/spl times/.
This paper reviews the circuit enablement activity conducted inside IBM's SiGe BiCMOS and RFCMOS technology enablement group. Examples of circuit designs are given. Model/hardware correlations on DC, AC, noise and nonlinearity performance are used to evaluate the BSIM3V3 modeling accuracy. Benchmark circuit example of a VCO is given to demonstrate the(More)
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