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  • R. Reis
  • 2008
The research and development of the design automation of integrated circuits started by the layout level and it evolved to higher levels of abstraction. At physical design level the evolution of automation was remained at the standard cell approach, where the layout of the cells are designed and included in a cell library. So, the design of the cell layout(More)
This work compares two fault tolerance techniques, Hamming code and Triple Modular Redundancy (TMR), that are largely used to mitigate Single Event Upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in VHDL and tested in two target applications: arithmetic circuits with pipeline and registers files.(More)
The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (Systems on Programmable Chip, or SoPCs). When deployed(More)
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