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This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully(More)
A 128 Mb 0.07 &#x03BC;m<sup>2</sup> 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two(More)
In this work we have demonstrated, for the first time, a 0.605&#x00B5;m<sup>2</sup> dual core oxide (DCO) dual Vdd 8T SRAM cell in 45LPG triple gate oxide CMOS process for use as L1 cache for high(More)
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