Quincy Lee

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1Mbit SRAM macro with adaptive leakage current reduction scheme is implemented in 28nm high-k metal gate CMOS technology. A current limiter that limits cell array leakage current at various process-voltage-temperature (PVT) corners is included in the proposed scheme. The leakage current is reduced by more than 60% at fast process corners by increasing(More)
A method for direct measurements of bit-line (BL) swing, sense amplifier (SA) offset and word-line (WL) pulse width is demonstrated in a 40nm CMOS 32kb fully functional SRAM macro with <2% area penalty. This allows, for the first time, deciding the best tuning option for WL-pulse (WLP) width based on the results being measured on site for BL swing(More)
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