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High-performance input queued switches achieve good performance with low cost. However, with the appearance of optical techniques, the line rate is much higher than before. Scheduling algorithms require not only good performance in delay and stability but fast speed and simple implementation as well. A variety of scheduling algorithms for Virtual Output(More)
Abstracl-This paper presents a novel scalable scheduling architecture for high-performance crossbar-based switches with virtual output queuing (VOQ) scheme. In contrast to traditional switching architectures where the scheduler is implemented by one single centralized scheduling device, the proposed scheduling architecture connects several small scheduling(More)
This paper describes a fine resolution, good linearity, and high throughput time-to-digital converter (TDC), which has realized in 0.18um CMOS technology. Based on a two-channel Vernier delay line (VDL) structure and an asynchronous pipelined readout circuitry, the TDC can achieve a maximum throughput of 500MS/s, a time resolution of 10ps and a total(More)
This paper presents a 10ps 500MHz time-to-digital converter (TDC) in 0.18μm CMOS technology. Based on the Vernier delay line structure, the TDC can achieve high resolution, high speed and a dynamic range of 0 ~ 640ps. To increase the accuracy, the delay line cells are designed using full-custom design method. Additional, the delay cells are divided(More)
This paper presents a 10Gb/s concatenated BCH encoder of super FEC. The concatenated BCH encoder module contains 32 BCH column encoder groups and 2 BCH row encoder groups. To achieve high speed, parallel encoding technique is employed. In addition, some optimization methods such as sub-expression sharing and tree-based structure are also adopted to balance(More)
This paper presents a 6.25Gbps adaptive 2-tap decision feedback equalizer (DFE) for serial backplane receiver. The proposed DFE can be used to reduce the effects of inter-symbol interference (ISI) and compensate the loss of the limited bandwidth channel. To meet the high speed requirement, the DFE is constructed in a half rate structure and most of the(More)
This paper presents a programmable frequency divider based on standard cell for digital video broadcasting-terrestrial (DVB-T) and other modern communication systems. As one of the components of PLL frequency synthesizer, this PFD cooperating with a dual-modulus prescaler can realize integer frequency division from 926 to 1381. The main steps of this(More)