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The design of SoC system, random test is becoming an application for IP cores verification gradually. In order to test the integrated EMIF IP core, the restricted random verification method is used with added flexible generation of parameterized script files and adaptable random test points. Based on the verification environment built, some tasks were(More)
approved: Gábor C. Temes Delta-Sigma () analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT(More)
A 0.8V 3rd-order ∆Σ DAC with headphone driver is presented. The circuit requires only one opamp per channel, shared by the internal DAC, the FIR and 2nd-order Sallen-Key low-pass filter, as well as by the headphone driver. The prototype IC implemented in a 0.35µm CMOS process achieved 88dB dynamic range (DR), while consuming 2.6mW from a 0.8V supply.
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