Learn More
Phase change memory (PCM) has been widely studied as a potential DRAM alternative. The multi-level cell (MLC) can further increase the memory density and reduce the fabrication cost by storing multiple bits in a single cell. Nevertheless, large write power, high write latency, as well as reliability issue resulted from the resistance drift, bring in(More)
Processing-in-memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die-stacking technology, we propose to leverage the unique features of(More)
—Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal(More)
3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel ω-LAT coding scheme to reduce the capacitive crosstalk and minimize the(More)
  • Friday, Blockinalex Blockinjones, +131 authors Qiaosha Zou
  • 2014
4 Welcome Welcome to the 24th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2014 held in Houston, Texas. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality BLOCKINin BLOCKINall BLOCKINareas BLOCKINrelated BLOCKINto BLOCKINVLSI, BLOCKINdevices BLOCKINand BLOCKINsystem BLOCKINlevel BLOCKINdesign. BLOCKINThe(More)
The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between the through-silicon vias (TSVs) and silicon substrate, and the presence of elevated thermal gradients. To address the stress issue, we propose a thorough(More)
—As one of the most promising solutions to the well-known interconnect crisis, three-dimensional (3D) integration attracts plenty of attention from both academia and industry communities. 3D integration techniques enable much shorter interconnect wire length, much higher memory bandwidth, and heterogeneous integration. These benign effects lead to a variety(More)
Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design(More)
—As the number of processing elements increases in a single chip, the interconnect backbone becomes more and more stressed when serving frequent memory and cache accesses. Network-on-Chip (NoC) has emerged as a potential solution to provide a flexible and scalable interconnect in a planar platform. In the mean time, three-dimensional (3D) integration(More)
—The emerging three-dimensional integrated circuit (3D IC) provides a promising solution for sustainable computer performance scaling. However, the high cost due to the complex pre-bond/intermediate testing and the low compound yield hinder the commercial adoption of 3D ICs. The defect clustering is found biasing the yield prediction, resulting in an(More)