Qianwen Chen

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Interfacial reliability is a challenging issue in through-silicon-via (TSV) technique. To accurately investigate the interfacial reliability of TSV, this paper developed an analytical solution approach, in which the effects of the liner are considered. The validity of the analytical solution is executed by comparison with finite element simulation results.(More)
Since the conventional planar ICs encountered many physical, technological and economic bottlenecks, 3D integration by stacking and connecting function blocks in a vertical fashion is regarded as a viable approach to alleviate such bottlenecks. Through-strata-via (TSV) is one of the most attractive 3D integration solutions, which offers a massive number of(More)
A split-gate structure of power VDMOS is proposed in this paper. The p-base of the split-gate VDMOS is formed by self-aligned ion implanted. Only five masks is used to fabrication while the performance of the split-gate VDMOS is better than the conventional VDMOS. Compared to present structure, the split-gate structure can effectively reduce the device(More)
In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details(More)
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