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The <i>maximum disjoint subset (MDS)</i> of rectangles is a subset of non-overlapping rectangles with the maximum total weight. The problem of finding the <i>MDS</i> of general rectangles has been proven to be NP-complete in [6]. In this paper, we focus on the problem of finding the <i>MDS</i> of boundary rectangles, which is an open problem and is closely(More)
As minimum feature size keeps shrinking, and the next generation lithography (e.g, EUV) further delays, double patterning lithography (DPL) has been widely recognized as a feasible lithography solution in 20nm technology node. However, as technology continues to scale to 14/10nm, DPL begins to show its limitations and usually generates too many undesirable(More)
In order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. Devices are split into smaller ones and placed with a common center point. We will address this problem of handling common centroid constraint in placement. A new representation called <i>Center-based Corner Block(More)
—Energy efficiency has become a very important issue to be addressed in today's system-on-a-chip (SoC) designs. One way to lower power consumption is to reduce the supply voltage. Multisupply voltage (MSV) is thus introduced to provide flexibility in controlling the power and performance tradeoff. In region-based MSV, circuits are partitioned into " voltage(More)
In this paper, we introduce and study the Rectangle Escape Problem (REP), which is motivated by PCB bus escape routing. Given a rectangular region <i>R</i> and a set <i>S</i> of rectangles within <i>R</i>, the REP is to choose a direction for each rectangle to escape to the boundary of <i>R</i>, such that the resultant maximum density over <i>R</i> is(More)
Conventional CMOS devices are facing an increasing number of challenges as their feature sizes scale down. Graphene nanoribbon (GNR) based devices are shown to be a promising replacement of traditional CMOS at future technology nodes. However, all previous works on GNRs focus at the device level. In order to integrate these devices into electronic systems,(More)
As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches,(More)
At the 10 nm technology node, the contact layers of integrated circuits (IC) designs are too dense to be printed by single exposure using 193 nm immersion (193<i>i</i>) lithography. Among all the emerging patterning approaches, block copolymer directed self-assembly (DSA) is a promising candidate with high throughput and low cost for sub-20 nm features.(More)
Self-aligned double patterning (SADP) lithography is a leading technology for 10<i>nm</i> node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges(More)