• Publications
  • Influence
Associative memory realized by a reconfigurable memristive Hopfield neural network.
Although synaptic behaviours of memristors have been widely demonstrated, implementation of an even simple artificial neural network is still a great challenge. In this work, we demonstrate theExpand
  • 120
  • 5
A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links
  • Q. Yu, P. Ampadu
  • Mathematics, Computer Science
  • IEEE Transactions on Circuits and Systems II…
  • 2011
We propose an error control method to comanage transient and permanent errors in the data link and physical layers of a network-on-chip (NoC). To reduce energy overhead, a configurable error controlExpand
  • 21
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A hardened network-on-chip design using runtime hardware Trojan mitigation methods
Due to the globalized semiconductor business model, malicious hardware modifications, known as hardware Trojans (HTs), have risen up as a big concern for chip security. HT detection and mitigationExpand
  • 17
  • 4
Adaptive error control for nanometer scale network-on-chip links
  • Q. Yu, P. Ampadu
  • Computer Science
  • IET Comput. Digit. Tech.
  • 3 November 2009
The authors present an adaptive error control method for switch-to-switch links in nanoscale networks-on-chip to manage reliability, throughput and energy. Unlike previous works, the proposed methodExpand
  • 25
  • 2
Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs
Circuit camouflaging is a layout-level technique to thwart image analysis-based reverse engineering attacks. An efficient dummy contact-based camouflaging method for monolithic 3-D integratedExpand
  • 12
  • 2
Security Threats in Approximate Computing Systems
Approximate computing systems improve energy efficiency and computation speed at the cost of reduced accuracy on system outputs. Existing efforts mainly explore the feasible approximation mechanismsExpand
  • 10
  • 2
A Flexible Parallel Simulator for Networks-on-Chip With Error Control
  • Q. Yu, P. Ampadu
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 2010
This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error controlExpand
  • 25
  • 1
Assessing CPA resistance of AES with different fault tolerance mechanisms
Countermeasures for Advanced Encryption Standard (AES) to thwart side-channel attack and fault attack are typically investigated in a separate fashion. There is lack of thorough investigation on howExpand
  • 25
  • 1
Hardware security assurance in emerging IoT applications
The Internet of Things (IoT) offers a more advanced service than a single device or an isolated system, as IoT connects diverse components, such as sensors, actuators, and embedded devices throughExpand
  • 25
  • 1
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration
We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing,Expand
  • 28
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